The present invention relates to the electronic circuit simulation art. Specifically, a method is described for compressing the event trace information which is generated during the simulation of an electronic circuit.
Circuit design verification is utilized by logic design engineers to test an electronic circuit design before it is reduced to a silicon device. The circuit designer creates functional logic which may be modeled so that various circuit stimuli may be applied to the circuit while monitoring and recording the circuit response. The simulation of functional logic may be done on a time basis, such as clock cycle by clock cycle, which permits observation of the functional logic over time.
The simulators which operate on a clock cycle basis usually employ a debug capability. The debugging tools that accompany circuit simulation equipment include a scope function which permits the designer to see the changing values during any cycle of the simulation. During simulation, a file may be created identifying the events which take place for each clock cycle. Events represent a change in value of a given facility. Each observed event in the simulation, representing a change in value for the facility, is recorded along with its value for each clock cycle to create a historical record of all events which is used in evaluating and debugging the functional logic.
The debugging tools are capable of specifying a particular facility, and clock cycle which may be of interest for analysis. The tool permits the analysis of the value of the faults for the selected clock cycle facilitating debugging of the functional logic which has been simulated.
The all events trace file may contain data for greater than 1 million facilities for hundreds of thousands of different clock cycles. The size of the resulting all events trace file will typically require several hundred megabytes of DASD space for storage. The sheer size of the all events trace (AET) file necessarily means that access to a facility value of a clock cycle is slow. Thus, it would be desirable to not only reduce the size of the AET file, but to maintain a high degree of access to the reduced AET file.
The reduction of the size of an AET file is accomplished using various compression utilities which compress the data once it is generated by the simulator. When using the debugging tools, the data is uncompressed and made available for the debugging tool. The compression of the AET file considerable reduces the amount of the storage space required for the file, however, it dramatically increases the time to store and access the data, slowing down the simulation and debugging process.
Optimization of the AET format reduces the storage requirements by eliminating unnecessary data. Since time and facility values need the most amount of storage, the time or clock cycle number is only kept when a value has changed for any facility in the AET file.
A change mask locates values of facilities that change, so that only changed values get stored, further cutting down on the size of the AET file.
While the foregoing does reduce the size of the AET file, access time suffers in that to locate the value of a given facility at a given time or clock cycle, the entire AET file has to be traversed, essentially recreating the uncompressed file. It is even possible, given the distribution of changes in values of a facility throughout an AET, that the resulting AET may be larger than the original AET.
The foregoing disadvantages are addressed by a method in accordance with the invention.